The present invention relates to a method for adjusting a temperature in a resist process after the exposure of at least one semiconductor wafer.
With continuously decreasing feature sizes in semiconductor wafer manufacturing, the influence with respect to accuracy of detail processes other than exposure on a lithographic track are growing more and more important.
The sequence of detail process steps on a lithographic track typically starts with depositing an adhesive substance, e.g. HMDS (hexamethyl disilazane), followed by coating the semiconductor wafer with a resist having a thickness of 0.3-5 xcexcm, depending on the technology used. After stripping the resist off of the backside and the edges of the wafer, a prebake step with a temperature of, e.g., 80-100xc2x0 C. is applied to the wafer for improving the adhesion and for hardening the resist.
After prebakexe2x80x94also called softbakexe2x80x94the exposure of the photo sensitive resist with a pattern projected from a mask or reticle in a wafer stepper or scanner is performed.
A resist process is then started by applying a post-exposure bake with typical temperatures of 100-110xc2x0 C., which is intended to generate a small flow of resist for smoothing out periodic intensity modulation due to interference effects. Those are produced by a possible back-reflection from a layer that underlies the resist layer and results in generating stationary waves.
In a development step, chemically altered resist materialxe2x80x94due to a photo-chemical reactionxe2x80x94is removed in case of a positive photo resist, thereby leaving behind a pattern structure in the resist layer.
In order to increase the resistance of the photo resist layer against the following etching step depending on its aggressivity, a temperature of about 120xc2x0 C. is applied to the resist for a third time known as the post-bake step. This step may be replaced by UV-hardening.
When using a chemically amplified resist, the temperatures applied may considerably deviate from the values given above. Chemically amplified resists are often used for an exposure wave length of 248 nm and below.
The final processes are etching, thereby transferring the resist pattern into the desired layer, or implantation followed by stripping off the resist. As is clearly visible from the process steps described, the temperature treatment is a critical issue on the lithographic track. Typically, there are small temperature windows with a lower temperature limit given by, e.g. a glassy point for which the desired function of the resist becomes active, and an upper limit at which plastic resist flow sets in. Further requirements are the reduction of water absorption and adhesion improvement.
Unfortunately, particularly the upper limit of the temperature represents a smooth limit and the disadvantageous effect of resist flow may already become apparent at moderate temperatures, e.g. during post-exposure bake, if particularly small feature sizes will be patterned into the resist.
Investigations related to quantifying this effect on line shapes can be found, e.g., in xe2x80x9cSelective modification of resist sidewall profiles with a post development bakexe2x80x9d, IBM Technical Disclosure Bulletin, Vol. 32, 1989, pages 141-145, XP 000049332, wherein line shape profiles are measured as a function of post exposure bake temperature. In addition, reference can be made to Young-Soo Sohn et al., xe2x80x9cEffect of temperature variation during post exposure bake on 193 nm chemically amplified resist simulationxe2x80x9d, Digest of papers Microprocesses and Nanotechnology, 2000, Society of Applied Physics, Japan, XP 001051557, which describes the performance of critical dimension measurements of lines structured in a resist, which have each experienced different temperatures.
Moreover, processes are adapted to fixed values of the temperature setup and in order to maintain uniformity from wafer to wafer, temperature deviations have to be particularly small, e.g. below 1xc2x0 C.
In order to improve the temperature treatment of the different baking steps, a system for uniform heating of a photo resist is provided in U.S. Pat. No. 6,034,771. In this teaching, radiation is applied to the photo resist, and an actual temperature of the resist can be determined from a measurement of the reflected light. Given this temperature information, a deviation from a desired value can be calculated and a temperature adjustment can be performed using heating lamps that irradiate heating light onto the resist. The temperature is thereby determined indirectly from a relationship between, e.g. resist thickness and temperature, or resist absorption and temperature, which has to be known a priori.
Unfortunately, it is not clear whether such a relationship remains constant during the different processing steps, thereby providing sufficient accuracy to adjust the temperature.
It is accordingly an object of the invention to provide a method for adjusting the temperature in a resist process which overcomes the above-mentioned disadvantages of the prior art methods of this general type.
It is a primary objective of the present invention to improve the temperatures during different baking steps in a resist process in order to adhere to wafer specification tolerances, and to thereby improve the wafer yield on the lithographic track.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for adjusting a temperature in a resist process. The method includes: providing at least a first semiconductor wafer coated with a resist; and providing a reticle test pattern including at least one pad structure having a first critical dimension and at least one antenna structure having a second critical dimension. The antenna structure is connected to the pad structure and the first critical dimension is at least 1.5 times the second critical dimension. The method also includes: exposing the first semiconductor wafer by projecting the pattern onto the resist to configure the pattern into the resist; performing a first resist process on the first semiconductor wafer while applying a first temperature; and determining a first sidewall angle of the pattern in the resist on the first semiconductor wafer by:
a) obtaining a first measured value by measuring the second critical dimension of the antenna structure,
b) obtaining a second measured value by measuring the first critical dimension of the pad structure, and
c) comparing the first measured value and the second measured value.
The method then includes: issuing a first signal, if the first sidewall angle exceeds a pre-defined threshold value; and adjusting the temperature of the resist process in response to the first signal.
In accordance with an added feature of the invention, the method includes: providing at least a second semiconductor wafer coated with a resist; exposing the second semiconductor wafer to configure the pattern in the resist on the second semiconductor wafer; performing a second resist process on the second semiconductor wafer with a second temperature that is different from the first temperature; measuring a second sidewall angle of the pattern in the resist on the second semiconductor wafer; comparing the first sidewall angle and the second sidewall angle; issuing a second signal, if the difference between the first sidewall angle and the second sidewall angle exceeds a pre-defined difference threshold value; and adjusting the temperature of the resist process in response to the second signal.
In accordance with an additional feature of the invention, the the pattern in the resist on the first semiconductor wafer is structured within a scribeline area of the first semiconductor wafer; and the pattern in the resist on the second semiconductor wafer is structured within a scribeline area of the second semiconductor wafer.
In accordance with another feature of the invention, the step of determining the first sidewall angle is performed by using a scanning electron microscope, an interferometer, and/or a scatterometer.
In other words, objective of the present invention is solved by a method for adjusting a temperature in a resist process after an exposure of at least one semiconductor wafer. The method includes steps of: providing at least a first semiconductor wafer coated with a resist, exposing the first semiconductor wafer with a projected reticle test pattern, performing a first resist process on the first semiconductor wafer, applying a first temperature, measuring a first sidewall angle of the pattern in the resist on the first semiconductor wafer, issuing a signal if the first resist sidewall angle exceeds a pre-defined threshold value, and adjusting the temperature of the resist process in response to the signal.
The sidewall angle measurement also denotes a critical dimension measurement of the resist sidewall. The critical dimension of a structure used here is the metric distance between two points, e.g. edges of a structure, in the plane of the waferxe2x80x94or reticle. With a known vertical resist thickness, the sidewall angle has a tight correlation with the critical dimension of the sidewall.
According to the present invention, there is underlying the perception that the impact of resist flow also depends on the extent of the resist pattern. Thus, advantage is taken of measuring the sidewall angle at resist edges at structures having different feature sizes. By measuring the sidewall angle, the direct impact of temperature deviations is measured by a decrease in the corresponding critical dimension of the corresponding complementary structure, e.g. a clear line with resist being removed from it bordering a larger resist pad.
Larger pads of resist include a stronger heat capacity, i.e. provide a stronger flow of resist as compared with thin lines, which in the case of too high temperatures cool faster in an adjacent cooling and do not provide that much flowing material that enters the clear lines.
Therefore, it may occur that the temperature setup of, e.g. the post-bake step is already adapted to small feature sizes, but thereby disregarding the bad impact of resist flow from larger resist pads into clear lines or pads at the same temperature. Therefore, measuring the sidewall angle of the transition area between the resist and the clear space after the development of test patterns, which are suited to the pattern representing the integrated circuit to be structured, provides a particularly advantageous method.
The problems that can be directly addressed by the present invention that originate from resist flow due to temperatures that are chosen to be too high include:
a change of the etch bias;
an etch attack of underlying layers;
unexpected implantation by missing depth uniformity;
overlay problems due to asymmetric sidewall angles, e.g. if there is a large resist pad on one side of a clear line and a thin resist line on the other side, thus leading to a pattern shift; and
critical dimension measurement problems.
These problems are cured by detecting the sidewall angles and comparing them with previously set threshold values. These threshold values are set to guarantee a neglectable resist flow for any structure sizes on the pattern that will be projected onto the resist.
In an aspect of the present invention, at least two, preferably a series of measurements are performed for each wafer to obtain a sidewall angle as a function of temperature. Starting with a temperature that is known to lie well within the allowed range for the temperature setup and then increasing the applied temperature stepwise for each wafer (e.g. by a constant difference), the curve of such a function will generally increase monotonically, and therefore exceed the given threshold value at a critical temperature. The temperature such determined is then used as the pattern and process dependent maximum temperature for the temperature setup of the resist process.
Preferably, prior to starting a set of production wafers, a test-reticle providing a variety of combinations of pad and antenna structures is used to measure a sequence of sidewall angles as a function of temperature. The test patterns on the reticle are a combination of a resist pad supplied with one or more antennas, the critical dimensions of which represent the variety of critical dimensions provided on the production pattern which are subsequently processed. Thus, advantageously, the impact of the resist pad extent on resist flow for different temperatures can easily be measured, detected and used for adjusting the temperature of the actual resist process. Examples of test patterns are given in the embodiments below.
It is also possible to provide these test patterns with the integrated circuit pattern, but positioned in the scribeline area as in the case of conventional metrology marks. In both casesxe2x80x94i.e. the series of test wafers inspected in advance of production wafers, or the test patterns defined in the scribe line area of production wafersxe2x80x94the test sites are inspected and measured after the corresponding bake step by using, a scanning electron microscope (SEM), an interferometer, or a scatterometer, for example. Particularly in the latter case, the sidewall angles have a deep impact on scattered or defracted light that is detected by the scatterometer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Method for adjusting a temperature in a resist process, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.